Altera JNEye Manuel d'utilisateur télécharger pdf (Page 175)

Figure 3-24: TP4 Hybrid Eye Diagram Measured with CDR Recovered Clock and PCI-Express 8GT

Receiver Eye Diagram Mask

When you enable a CDR in a receiver, the reference clock’s phase noise is shaped and filtered with the

CDR’s response. The following figure shows the characteristics of phase noise at the output of the

reference clock (blue), after transmitter PLL (red), after transmitter PLL plus transmitter’s intrinsic jitter

(red), after RX CDR (cyan), and after RX CDR with transmitter and receiver’s intrinsic jitter (black). The

associated random jitter from the phase noise power spectrum at each of the above stages are calculated

and displayed in the text below the plot.

3-24

Analysis

UG-1146

2015.05.04

Altera Corporation

Tutorial: PCI Express 8GT

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Altera JNEye Manuel d'utilisateur Page 175