Altera HyperTransport MegaCore Function Manuel d'utilisateur Page 8
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1–4 Chapter 1: About this MegaCore Function
Performance
HyperTransport MegaCore Function User Guide © November 2009 Altera Corporation
Preliminary
Table 1–4 shows performance and device utilization for the HyperTransport
MegaCore function in Stratix II and Stratix II GX devices.
Table 1–5 shows performance and device utilization for the HyperTransport
MegaCore function in Stratix and Stratix GX devices.
Table 1–4. HyperTransport MegaCore Function Performance in Stratix II and Stratix II GX Devices
Parameters
Combinational
ALUTs
(2)
Logic
Registers
Memory
HT Link
f
MAX
(MHz)
(3)
User
Interface
f
MAX
(MHz)
(3)
Rx
Posted
Buffers
Rx
Non-Posted
Buffers
Rx
Response
Buffers
Clocking
Option (1) M4K M512
84 4Shared
Rx/Tx/Ref
3,500 5,200 12 0 500 125 (4)
84 4Shared
Ref/Tx
3,500 5,200 14 0 500 125 (4)
84 4Shared
Rx/Tx
3,600 5,400 16 0 500 > 150
88 8Shared
Rx/Tx
4,000 6,000 16 0 500 > 150
16 8 8 Shared
Rx/Tx/Ref
4,100 6,200 12 0 500 125 (4)
16 8 8 Shared
Ref/Tx
4,100 6,200 14 0 500 125 (4)
16 8 8 Shared
Rx/Tx
4,200 6,400 16 0 500 > 150
Notes to Table 1–4:
(1) Refer to “Clocking Options” on page 3–7 for more information about these options.
(2) Other parameters (BAR configurations, etc.) vary the ALUT and Logic Register utilization numbers by approximately +/- 200.
(3) Figures for -3 speed grade devices only.
(4) When using the Shared Rx/Tx/Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the HT frequency divided by
four.
Table 1–5. HyperTransport MegaCore Function Performance in Stratix and Stratix GX Devices
Parameters Utilization HT Link f
MAX
(MHz)
User Interface f
MAX
(MHz)
Rx
Posted
Buffers
Rx
Non-Posted
Buffers
Rx
Response
Buffers
Clocking Option
(1)
LEs
(2)
M4K
Blocks
Speed Grade
-5 -6 -5 -6
8 4 4 Shared Rx/Tx/Ref 7,500 12 400 400 100 (3) 100 (3)
8 4 4 Shared Ref/Tx 7,600 14 400 400 100 (3) 100 (3)
8 4 4 Shared Rx/Tx 7,900 16 400 400 > 125 > 100
8 8 8 Shared Rx/Tx 8,900 16 400 400 > 125 > 100
16 8 8 Shared Rx/Tx/Ref 9,400 12 400 400 100 (3) 100 (3)
16 8 8 Shared Ref/Tx 9,500 14 400 400 100 (3) 100 (3)
16 8 8 Shared Rx/Tx 9,700 16 400 400 > 125 > 100
Notes to Table 1–5:
(1) Refer to “Clocking Options” on page 3–7 for more information about these options.
(2) Other parameters (BAR configurations etc.) vary the LE utilization by approximately +/- 200 LEs.
(3) When using the Shared Rx/Tx/Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the HT frequency divided by four.
- User Guide 1
- UG-MCHYPRTRNS-1.12 2
- Contents 3
- Appendix C. Example Design 4
- Additional Information 4
- Release Information 5
- Device Family Support 5
- Introduction 6
- Features 6
- Performance 7
- Notes to Table 1–4: 8
- Notes to Table 1–5: 8
- 2. Getting Started 9
- MegaCore Function Walkthrough 10
- Step 1: Parameterize 13
- Step 2: Set Up Simulation 17
- Figure 2–9. Set Up Simulation 18
- Step 3: Generate 19
- Notes to Table 2–1: 20
- Compile the Design 21
- Simulate the Design 21
- Program a Device 22
- Set Up Licensing 23
- Example Quartus II Project 24
- ■ input_ht_vector.dat 25
- ■ output_ht_vector.dat 25
- ■ input_ui_vector.dat 25
- ■ output_ui_vector.dat 25
- About the Test Vectors 26
- 3. Specifications 27
- HT Systems 28
- HT Flow Control 29
- Physical Interface 30
- Protocol Interface 31
- End-Chain Handler 32
- Rx Claimed Buffers 32
- Tx Buffers 32
- Scheduler 32
- Clocking Options 33
- Shared Rx/Tx Clock 34
- Shared Ref/Tx Clock 34
- Chapter 3: Specifications 3–9 35
- Preliminary 35
- Shared Rx/Tx/Ref Clock 36
- Note to Figure 3–8: 37
- HT Link Rx Signals 42
- HT Link System Signals 42
- HT Link Tx Signals 42
- Notes to Table 3–6: 45
- Notes to Figure 3–10: 46
- Notes to Figure 3–11: 46
- Notes to Figure 3–12: 47
- Notes to Figure 3–13: 47
- Notes to Table 3–8: 51
- Addr[39:8] 52
- Notes to Figure 3–16: 53
- Notes to Figure 3–17: 53
- Notes to Figure 3–18: 54
- User Interface System Signals 55
- Using PLL Resets 55
- CSR Interface Signals 56
- CSR Module 57
- Notes to Table 3–13: 58
- Notes: to Table 3–16: 60
- A. Parameters 67
- Base Address Registers 68
- Advanced Settings 69
- A–4 Appendix A: Parameters 70
- Parameter Lists 70
- Guidelines 71
- C. Example Design 73
- General Description 74
- Typographic Conventions 76
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