Altera Cyclone V E FPGA Development Board Manuel d'utilisateur Page 52
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- Table des matières
- MARQUE LIVRES
- Reference Manual 1
- Contents 3
- Additional Information 4
- 1. Overview 5
- Board Component Blocks 6
- Chapter 1: Overview 1–3 7
- Handling the Board 8
- 2. Board Components 9
- Board Overview 10
- Handbook 12
- I/O Resources 13
- FPGA Configuration 18
- Note to Table 2–6: 21
- Figure 2–4. PFL Configuration 22
- Status Elements 23
- Setup Elements 24
- Board Settings DIP Switch 25
- JTAG Chain Control DIP Switch 25
- CPU Reset Push Button 25
- Clock Circuitry 26
- General User Input/Output 28
- General LEDs 29
- HSMC LEDs 30
- Debug Header 31
- Components and Interfaces 32
- RS-232 Serial UART 38
- USB-UART 39
- DDR3 SDRAM 40
- LPDDR2 SDRAM 43
- Synchronous SRAM 46
- Power Supply 49
- Power Distribution System 50
- Power Measurement 51
- 3. Board Components Reference 53
- Notes to Table 3–2: 54
- Note to Table: 55
- Typographic Conventions 56
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