Altera Cyclone V E FPGA Development Board Manuel d'utilisateur télécharger pdf (Page 48)

2–40 Chapter 2: Board Components

Memory

Cyclone V E FPGA Development Board March 2013 Altera Corporation

Reference Manual

FLASH_CLK

N12 2.5-V Clock

FLASH_OEN

L11 2.5-V Output enable

FLASH_RDYBSYN

J12 2.5-V Ready

FLASH_RESETN

K11 2.5-V Reset

FLASH_WEN

P12 2.5-V Write enable

FLASH_WPN

— 2.5-V Write protect

FSM_A1

B11 2.5-V Address bus

FSM_A2

A11 2.5-V Address bus

FSM_A3

D9 2.5-V Address bus

FSM_A4

C10 2.5-V Address bus

FSM_A5

A10 2.5-V Address bus

FSM_A6

A9 2.5-V Address bus

FSM_A7

C9 2.5-V Address bus

FSM_A8

B8 2.5-V Address bus

FSM_A9

B7 2.5-V Address bus

FSM_A10

A8 2.5-V Address bus

FSM_A11

B6 2.5-V Address bus

FSM_A12

A6 2.5-V Address bus

FSM_A13

C7 2.5-V Address bus

FSM_A14

C6 2.5-V Address bus

FSM_A15

F13 2.5-V Address bus

FSM_A16

E13 2.5-V Address bus

FSM_A17

A5 2.5-V Address bus

FSM_A18

A4 2.5-V Address bus

FSM_A19

J7 2.5-V Address bus

FSM_A20

H7 2.5-V Address bus

FSM_A21

J9 2.5-V Address bus

FSM_A22

H9 2.5-V Address bus

FSM_A23

G9 2.5-V Address bus

FSM_A24

F8 2.5-V Address bus

FSM_A25

E8 2.5-V Address bus

FSM_A26

D8 2.5-V Address bus

FSM_D0

F16 2.5-V Data bus

FSM_D1

E16 2.5-V Data bus

FSM_D2

M9 2.5-V Data bus

FSM_D3

M8 2.5-V Data bus

FSM_D4

F15 2.5-V Data bus

FSM_D5

E15 2.5-V Data bus

FSM_D6

E12 2.5-V Data bus

Table 2–28. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)

Board

Reference (U10)

Schematic Signal Name

Cyclone V E FPGA

Pin Number

I/O Standard Description

1 2 ... 43 44 45 46 47 48 49 50 51 52 53 54 55 56

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Altera Cyclone V E FPGA Development Board Manuel d'utilisateur Page 48

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