Altera Arria V SoC Development Board Manuel d'utilisateur Page 68
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- Table des matières
- MARQUE LIVRES
- Reference Manual 1
- Arria V SoC Development Board 1
- Contents 3
- Additional Information 4
- 1. Overview 5
- 1–2 Chapter 1: Overview 6
- Board Component Blocks 6
- Chapter 1: Overview 1–3 7
- Handling the Board 8
- 2. Board Components 9
- Board Overview 10
- Featured Device: Arria V SoC 13
- FPGA Configuration 18
- Figure 2–3. JTAG Chain 19
- Note to Table 2–5: 21
- Figure 2–4. PFL Configuration 22
- Status Elements 23
- Setup Elements 24
- JTAG Chain Control DIP Switch 25
- HPS Jumpers 26
- CPU Reset Push Button 26
- MAX V Reset Push Button 26
- General User Input/Output 27
- User-Defined DIP Switch 28
- User-Defined LEDs 28
- Clock Circuitry 29
- Off-Board Input/Output Clock 30
- Components and Interfaces 31
- Single-Port RGMII 33
- Micrel KSZ9021RN 33
- 10/100 Ethernet (FPGA) 34
- LMK_SYSREF_FMC_N 41
- LMK_SYSREF_FMC_P 41
- RS-232 UART (HPS) 44
- Real-Time Clock (HPS) 45
- C Interface 46
- DDR3 SDRAM (FPGA) 47
- DDR3 SDRAM (HPS) 53
- QSPI Flash (HPS) 58
- EPCQ Flash 58
- Synchronous Flash 59
- Micro SD Flash Memory 60
- Power Supply 61
- Power Distribution System 62
- Power Measurement 63
- 3. Board Components Reference 65
- Notes to Table 3–2: 67
- CE EMI Conformity Caution 68
- Note to Table: 69
- Typographic Conventions 70
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