Altera Arria V SoC Development Board Manuel d'utilisateur Page 58
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2–50 Chapter 2: Board Components
Memory
Arria V SoC Development Board July 2014 Altera Corporation
Reference Manual
QSPI Flash (HPS)
The development board supports one 1-Gb serial NOR flash device for non-volatile
storage of the HPS boot code, user data, and program. The device connects to the HPS
dedicated interface and may contain a secondary boot code.
This 4-bit data memory interface can sustain burst read operations at up to 108 MHz
for a throughput of 54 MBps. Erase capability is at 4 KB, 64 KB, and 32 MB.
Table 2–29 lists the QSPI flash pin assignments, signal names, and functions. The
signal names and types are relative to the Arria V SoC in terms of I/O setting and
direction.
EPCQ Flash
The development board supports one 256-Mb serial/quad-serial NOR flash device for
non-volatile storage of the FPGA configuration image. The device connects to the
FPGA dedicated interface through the IDTQS3861 device.
Table 2–30 lists the EPCQ flash pin assignments, signal names, and functions. The
signal names and types are relative to the MAX V CPLD 5M2210 System Controller in
terms of I/O setting and direction. Some pins are used in other interfaces as well due
to functionality sharing.
Table 2–29. QSPI Flash Schematic Signal Names and Functions
Board
Reference (U19)
Schematic
Signal Name
Arria V SoC Pin
Number
I/O Standard Description
16
QSPI_CLK
F15 3.3-V Clock
15
QSPI_IO0
D15 3.3-V Data bus
8
QSPI_IO1
G15 3.3-V Data bus
9
QSPI_IO2
M15 3.3-V Data bus
1
QSPI_IO3
H15 3.3-V Data bus
7
QSPI_SS0
N15 3.3-V Chip enable
3
MAX_QSPI_RSTN
— 3.3-V Reset
Table 2–30. EPCQ Flash Schematic Signal Names and Functions
Board
Reference (U28)
Schematic Signal Name I/O Standard Description
16
FPGA_DCLK
3.3-V Clock
15
FPGA_AS_DATA0
3.3-V Data bus
8
FPGA_AS_DATA1
3.3-V Data bus
9
FPGA_AS_DATA2
3.3-V Data bus
1
FPGA_AS_DATA3
3.3-V Data bus
7
FPGA_NCS0
3.3-V Chip enable
- Reference Manual 1
- Arria V SoC Development Board 1
- Contents 3
- Additional Information 4
- 1. Overview 5
- 1–2 Chapter 1: Overview 6
- Board Component Blocks 6
- Chapter 1: Overview 1–3 7
- Handling the Board 8
- 2. Board Components 9
- Board Overview 10
- Featured Device: Arria V SoC 13
- FPGA Configuration 18
- Figure 2–3. JTAG Chain 19
- Note to Table 2–5: 21
- Figure 2–4. PFL Configuration 22
- Status Elements 23
- Setup Elements 24
- JTAG Chain Control DIP Switch 25
- HPS Jumpers 26
- CPU Reset Push Button 26
- MAX V Reset Push Button 26
- General User Input/Output 27
- User-Defined DIP Switch 28
- User-Defined LEDs 28
- Clock Circuitry 29
- Off-Board Input/Output Clock 30
- Components and Interfaces 31
- Single-Port RGMII 33
- Micrel KSZ9021RN 33
- 10/100 Ethernet (FPGA) 34
- LMK_SYSREF_FMC_N 41
- LMK_SYSREF_FMC_P 41
- RS-232 UART (HPS) 44
- Real-Time Clock (HPS) 45
- C Interface 46
- DDR3 SDRAM (FPGA) 47
- DDR3 SDRAM (HPS) 53
- QSPI Flash (HPS) 58
- EPCQ Flash 58
- Synchronous Flash 59
- Micro SD Flash Memory 60
- Power Supply 61
- Power Distribution System 62
- Power Measurement 63
- 3. Board Components Reference 65
- Notes to Table 3–2: 67
- CE EMI Conformity Caution 68
- Note to Table: 69
- Typographic Conventions 70
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