Altera Arria II GX FPGA Development Board Manuel d'utilisateur Page 62
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- Table des matières
- MARQUE LIVRES
- Reference Manual 1
- Contents 3
- Additional Information 4
- 1. Overview 5
- Board Component Blocks 6
- Chapter 1: Overview 1–3 7
- Handling the Board 8
- 2. Board Components 9
- Board Overview 10
- I/O Resources 13
- Note to Table 2–4: 14
- Note to Table 2–5: 14
- Table 2–8 lists the MAX 19
- Configuration 20
- Figure 2–4. JTAG Chain 21
- Notes to Table 2–10: 24
- Status Elements 25
- Board Settings DIP Switch 26
- JTAG Chain Header 27
- Clock Circuitry 29
- Notes to Table 2–20: 30
- EP2AGX125EF35 31
- General User Input/Output 32
- General User-Defined LEDs 33
- HSMC User-Defined LEDs 34
- Note to Table 2–29: 34
- Components and Interfaces 36
- 10/100/1000 Ethernet 39
- High-Speed Mezzanine Cards 40
- DDR2 SODIMM 49
- Power Supply 57
- Power Distribution System 58
- Power Measurement 59
- Notes to Table 2–50: 60
- A. Board Revision History 61
- Note to Table: 63
- Typographic Conventions 64
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