Altera 100G Interlaken MegaCore Function Manuel d'utilisateur Page 106
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Additional Information
B
2015.05.04
UG-01128
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Document Revision History
Table B-1: 100G Interlaken MegaCore Function User Guide Revision History
Date ACDS
Version
Changes Made
2015.05.04 15.0
• Added new TX scrambler seed parameter in new section TX Scrambler
Seed on page 3-5. Previously this parameter was hidden (SCRAM_CONST)
and unavailable for Arria 10 devices. In the IP core version 15.0 and later,
you must modify the scrambler seed from the parameter editor.
• Improved description of itx_ifc_err output signal in 100G Interlaken IP
Core User Data Transfer Interface Signals on page 5-4.
• Improved description of itx_hungry output signal in 100G Interlaken IP
Core Interlaken Link and Miscellaneous Interface Signals on page 5-9.
• Updated filenames for hidden parameter editing to include the filenames
for Arria 10 variations, in Modifying Hidden Parameter Values on page
9-3.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
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ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About This MegaCore Function 3
- Device Family Support 6
- IP Core Verification 7
- Device Speed Grade Support 9
- Release Information 9
- Altera IP Core Release Notes 10
- OpenCore Plus IP Evaluation 11
- - HDL synthesis file 13
- 10 variation 14
- Pin Assignments 16
- Adding the External PLL 22
- 100G Interlaken IP Core 23
- Number of Lanes 25
- Meta Frame Length in Words 26
- Data Rate 26
- Enable M20K ECC Support 28
- Include Diagnostic Features 28
- Number of Calendar Pages 29
- TX Scrambler Seed 29
- Transfer Mode Selection 30
- Data Format 30
- Functional Description 31
- Management Interface 32
- High Level Block Diagram 34
- IP Core Reset 35
- Interleaved and Packet Modes 37
- Dual Segment Mode 38
- M20K ECC Support 40
- Device Dependent Signals 72
- Offset Name R/W Description 76
- Example Design 82
- Top Testbench 82
- Testbench Simulation Behavior 83
- Simulating the Example Design 84
- Internal Serial Loopback Mode 86
- External Loopback Mode 87
- CRC32 Error Injection 92
- CRC24 Error Injection 93
- Advanced Parameter Settings 94
- RXFIFO Address Width 95
- Subscribe 98
- UG-01128 100
- 2015.05.04 100
- Signal Name Direction Width 102
- Description 102
- Related Information 102
- Ethernet Traffic 103
- Altera Corporation 105
- Send Feedback 105
- Additional Information 106
- Date ACDS 107
- Changes Made 107
- How to Contact Altera 110
- Typographic Conventions 110
- Visual Cue Meaning 111
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