Altera 10-Gbps Ethernet MAC MegaCore Function Manuel d'utilisateur télécharger pdf (Page 145)

9–26 Chapter 9: Interface Signals

10-Gbps Ethernet MAC MegaCore Function User Guide February 2014 Altera Corporation

rx_path_delay_10g_data

(in 10 Gbps mode)

Input 16

Connect this bus to the Altera PHY IP. This bus

carries the path delay on the receive datapath. The

delay is measured between the physical network

and XGMII SDR. The delay is used to adjust the

ingress timestamp.

Consists of:

■ Bits 0 to 9: Fractional number of clock cycle

■ Bits 10 to 15: Number of clock cycle

rx_path_delay_1g_data

(in 1 Gbps, 10 Mbps, and 100 Mbps mode)

Input 22

Connect this bus to the Altera PHY IP. This bus

carries the path delay on the receive datapath. The

delay is measured between the physical network,

and GMII and MII. The delay is used to adjust the

ingress timestamp.

Consists of:

■ Bits 0 to 9: Fractional number of clock cycle

■ Bits 10 to 21: Number of clock cycle

Table 9–14. Path Delay Interface Signals

Signal Direction Width Description

1 2 ... 140 141 142 143 144 145 146 147 148 149 150 ... 174 175

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Altera 10-Gbps Ethernet MAC MegaCore Function Manuel d'utilisateur Page 145