Altera PHY IP Core Guide de l'utilisateur Page 175
- Page / 230
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Chapter 10: Transceiver Reconfiguration Controller 10–9
Reconfiguration Controller Memory Map
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Reconfiguration Controller Memory Map
This section describes the memory map that control reconfiguration and signal
integrity features. Each register-based feature has its own Avalon-MM address space
within the Transceiver Reconfiguration Controller as Figure 10–3 illustrates.
Table 10–8 lists the address range for the Transceiver Reconfiguration Controller and
the reconfiguration and signal integrity modules. It provides links to the sections
describing the registers in each module.
Figure 10–3. Memory Map of the Transceiver Reconfiguration Controller Registers
Direct Addressing
Address Offset
0x00
0x13
0x0B
0x1B
0x2B
0x33
0x3B
0x43
0x7F
Transceiver Reconfiguration Controller
Avalon-MM Interface
reconfig_mgmt_*
Avalon-MM
Registers
Signal Integrity
Features
DFE
ADCE
AT X
Tuning
MIF
Streamer
PLL
Reconfig
EyeQ
PMA
Analog
EyeQ
. . .
DFE
. . .
PMA
ADCE
. . .
AT X
. . .
Streamer
. . .
PLL
. . .
SM
Embedded
Controller
. . .
Table 10–8. Transceiver Reconfiguration Controller Address Map (Part 1 of 2)
Address Link
7’h08–7’h0C “PMA Analog Controls” on page 10–11
7’h10–7’h14 “EyeQ” on page 10–12
7’h18–7’h1C “DFE” on page 10–14
7’h28–7’h2C “AEQ” on page 10–16
7’h30–7’h34 “ATX PLL Calibration” on page 10–17
- User Guide 1
- Contents 3
- Chapter 7. Custom PHY IP Core 5
- Contents vi 6
- 1. Introduction 9
- Stratix V Device 10
- Reset Controller 11
- Avalon-MM PHY Management 11
- 1–4 Chapter 1: Introduction 12
- Unsupported Features 13
- 1–6 Chapter 1: Introduction 14
- 2. Getting Started 15
- Note to Figure2–2: 16
- Simulate the IP Core 18
- 3. 10GBASE-R PHY IP Core 19
- Release Information 20
- Note to Table 3–1: 21
- Stratix IV Devices 23
- Stratix V Devices 24
- SDR XGMII TX Interface 30
- Note to Table 3–9: 30
- SDR XGMII RX Interface 31
- Note to Table 3–11: 31
- Status Interface 32
- Clocks, Reset, and Powerdown 32
- Serial Interface 35
- Note to Table 3–15: 35
- TimeQuest Timing Constraints 40
- Note to Figure4–1: 43
- Note to Table 4–1: 44
- Advanced Options 51
- Configurations 52
- PMA Channel Controller 58
- Stratix IV GX Devices 65
- 5. Interlaken PHY IP Core 67
- Analog Settings 70
- Note to Figure5–2: 74
- Avalon-ST TX Interface 75
- Avalon-ST RX Interface 76
- PLL Interface 78
- TX and RX Serial Interface 78
- Optional Clocks for Deskew 78
- Transceiver Reconfiguration 81
- General Options 84
- Note to Figure6–2: 90
- PIPE Interface 92
- Note to Table 6–8: 93
- Transceiver Serial Interface 94
- Registers 95
- 7. Custom PHY IP Core 101
- Device Family Support 102
- Parameter Settings 103
- Word Alignment 106
- Rate Match FIFO 107
- 8B/10B Encoder and Decoder 108
- Byte Ordering 108
- PLL Reconfiguration 109
- Analog Options 110
- Presets for Ethernet 114
- Interfaces 115
- Note to Figure7–2: 116
- Clock Interface 118
- Status Signals (Optional) 118
- Note to Table 7–17: 119
- Register Interface 120
- Register Descriptions 121
- Dynamic Reconfiguration 124
- 8. Low Latency PHY IP Core 125
- Note to Table 8–4: 129
- Note to Table 8–5: 130
- Serial Data Interface 137
- Optional Status Interface 138
- PMA and Light-Weight PCS 139
- Arria V or Stratix V FPGA 143
- Auto-Negotiation 144
- Delay Estimation Logic 145
- Note to Figure9–2: 145
- Delay Numbers 146
- Note to Table 9–4: 147
- Additional Options 150
- TX and RX Status Signals 159
- Deterministic PHY IP Core 161
- Controller 167
- Note to Figure10–1: 169
- Note to Table 10–6: 174
- Embedded 175
- Offset Cancellation 176
- Duty Cycle Calibration 176
- PMA Analog Controls 177
- Pre-CDR Reverse Serial 178
- Loopback 178
- Post-CDR Reverse Serial 178
- ATX PLL Calibration 183
- Channel Reconfiguration 187
- Streamer Module 188
- Stratix V MIF 191
- Register-Based Write 193
- Register-Based Read 193
- Direct Write Reconfiguration 195
- Figure 10–6. Sample MIF 196
- Example 10–5. (continued) 197
- Notes to Figure 10–14: 205
- Transceiver 206
- XAUI PHY 209
- Port Differences 210
- Note to Table 11–3: 212
- Note to Table 11–5: 215
- Custom PHY 216
- Note to Table 11–6: 217
- Note to Table 11–7: 218
- Additional Information 219
- Revision History 220
- Note to Table: 228
- Typographic Conventions 229
Produits connexes et manuels pour Logiciel Altera PHY IP Core
Logiciel Altera UG-01080 Guide de l'utilisateur
(120 pages)
(120 pages)
Logiciel Altera DE2-115 Guide de l'utilisateur
(107 pages)
(107 pages)
Logiciel Altera UG-01080 Guide de l'utilisateur
(484 pages)
(484 pages)
© 2020, manymanuals.fr. Tous droits réservés | 0.044 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Commentaires sur ces manuels