Altera DE2-115 Manuel d'utilisateur télécharger pdf (Page 53)

Detailed information for using the ADV7123 video DAC is available in its datasheet, which can be

found on the manufacturer’s website, or in the DE2_115_datasheets\VIDEO-DAC folder on the

DE2-115 System CD. The pin assignments between the Cyclone IV E FPGA and the ADV7123 are

listed in Table 4-16. An example of code that drives a VGA display is described in Sections 6.2 and

6.3.

Note: The RGB data bus on DE2-115 board is 8 bit instead of 10 bit on DE2/DE2-70 board.

Figure 4-22 VGA horizontal timing specification

Table 4-14 VGA Horizontal Timing Specification

VGA mode Horizontal Timing Spec

Configuration Resolution(HxV) a(us) b(us) c(us) d(us) Pixel clock(MHz)

VGA(60Hz) 640x480 3.8 1.9 25.4 0.6 25

VGA(85Hz) 640x480 1.6 2.2 17.8 1.6 36

SVGA(60Hz) 800x600 3.2 2.2 20 1 40

SVGA(75Hz) 800x600 1.6 3.2 16.2 0.3 49

SVGA(85Hz) 800x600 1.1 2.7 14.2 0.6 56

XGA(60Hz) 1024x768 2.1 2.5 15.8 0.4 65

XGA(70Hz) 1024x768 1.8 1.9 13.7 0.3 75

XGA(85Hz) 1024x768 1.0 2.2 10.8 0.5 95

1280x1024(60Hz) 1280x1024 1.0 2.3 11.9 0.4 108

Table 4-15 VGA Vertical Timing Specification

VGA mode Vertical Timing Spec

Configuration Resolution(HxV) a(lines)

b(lines)

c(lines)

d(lines)

Pixel clock(MHz)

VGA(60Hz) 640x480 2 33 480 10 25

VGA(85Hz) 640x480 3 25 480 1 36

1 2 ... 48 49 50 51 52 53 54 55 56 57 58 ... 120 121

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Altera DE2-115 Manuel d'utilisateur Page 53