Altera Viterbi Compiler Manuel d'utilisateur Page 18
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- Table des matières
- MARQUE LIVRES
- Viterbi IP Core User Guide 1
- Contents 2
- Altera Corporation 3
- About the Viterbi IP Core 4
- DSP IP Core Verification 5
- Parameters 7
- Device ALM f 7
- Memory Registers 7
- Send Feedback 8
- OpenCore Plus IP Evaluation 10
- Related Information 11
- Search for installed IP cores 12
- UG-VITERBI 13
- 2014.12.15 13
- File Name Description 14
- DSP Builder Design Flow 17
- Convolutional Encoder 19
- Trellis Coded Modulation 20
- Trellis Decoder 22
- Viterbi IP Core Parameters 25
- BER Estimator 26
- Code Sets 27
- Viterbi Parameters 28
- Soft Symbol Input 29
- Test Data 30
- External Puncturing 31
- Global Signals 32
- Avalon-ST Sink Signals 32
- Signal Name 33
- Avalon-ST 33
- Direction Description 33
- Avalon Source-ST Signals 34
- Configuration Signals 35
- Status Signals 36
- With a different ending 38
- Document Revision History 39
- Date Version Changes Made 40
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