Altera Transceiver SI Manuel d'utilisateur Page 21
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Altera Corporation Getting Started User Guide 2–13
June 2006 Transceiver Signal Integrity Development Kit, Stratix II GX Edition
Getting Started
Figure 2–4 shows the jumper header connections and corresponding
VCCHTX values.
Figure 2–4. Jumper Header Connections and Corresponding VCCHTX Values
1 Before powering up the board, the VCCHTX jumper settings
should be specified.
The following list defines the analog setting parameters in the control
panel window:
■ VOD = output driver voltage
■ EQ = equalization
■ Gain = DC gain
■ PE = pre-emphasis
● In the PE setting list, Pre, 1
st
Post, and 2
nd
Post settings represent
different taps.
■ PDN = Setting the PDN performs a power down on the Quad.
Communication Settings
The top right-hand side of the control panel window provides the
following Communication settings:
■ Communication Cable—This list displays the different physical
interconnect options to communicate with the board. Currently, USB
Serial is supported.
3V3
7
8
1
3
2
8
LP38842MR-ADJ
S/D
ADJ
IN
U15
GND01
GND02
BACK
OUT
NC
BIAS
5V
VCCHTX
J20
BANANA_JACK_RED
Red
F6
CONN_3
J50
R45
16.9K
(1%)
C44
0.1µF
C49
4.7µF Tantalum
C52
10µF 0805
R46
10K
(1%)
R44
11.5K
(1%)
C54
130pF
C53
200pF
123
+
94
5
- Stratix II GX Edition 1
- Getting Started User Guide 1
- Part Number UG-SIDS2GX-1.0 2
- Contents 3
- 4 Altera Corporation 4
- Preliminary 4
- About this User Guide 5
- Typographic 6
- Conventions 6
- 1. About This Kit 7
- Documentation 8
- 2. Getting Started 9
- Check the Kit’s Contents 10
- Inspect the Board 10
- Hardware Requirements 11
- Software Requirements 12
- Software 13
- Installation 13
- Considerations 15
- Licensing 15
- Connect the 16
- Cables to the 16
- Board and 16
- Computer 16
- Setting the Clock 17
- Circuit Switches 17
- Pre-Defined Test Designs 18
- Demo Application GUI Tutorial 19
- Analog Settings 20
- Communication Settings 21
- Data Pattern Settings 22
- Serial Loopback Settings 23
- Reset Settings 23
- Link Control Settings 24
- Measuring 25
- Signal Eye 25
- Diagrams of 25
- Transmitted 25
- TDS 8000 Sampling Scope 27
- Basic_trig_clock 27
- Appendix A. Non-GUI Based 29
- Example Design 29
- General User 30
- Interfaces 30
- 7-Segment Display 31
- DIP Switches 31
- Push Button Switches 33
- Write and Read 34
- PMA Values 34
- Design Walkthrough 35
- Troubleshooting Solutions 36
- Debugging Using the SignalTap 36
- II Embedded Logic Analyzer 36
- Creating Your 37
- Custom Data 37
- Generators and 37
- Checkers 37
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