Altera Stratix V Avalon-MM Interface for PCIe Solutions manuels

Manuels d'utilisation et guides de l'utilisateur pour Instruments de mesure Altera Stratix V Avalon-MM Interface for PCIe Solutions.
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Altera Stratix V Avalon-MM Interface for PCIe Solutions Manuel d'utilisateur (184 pages)

marque: Altera | Catégorie: Instruments de mesure | Taille: 1.76 MB |

Table des matières

User Guide

Datasheet

Features

Interface

Release Information

Device Family Support

Altera FPGA

Debug Features

IP Core Verification

Recommended Speed Grades

Running Qsys

Generating the Example Design

Simulating Altera Designs

Time TLP Type Payload

TLP Header

Creating a Quartus II Project

Compiling the Design

Programming a Device

Parameter Settings

Parameter Value Description

Device Capabilities

Error Reporting

Link Capabilities

MSI and MSI-X Capabilities

Power Management

Clock Domains on page 6-5

Application Layer

RX Avalon-MM Master Signals

Clock Signals

Signal Direction Description

Variant Logical Interfaces

Hard IP Status Extension

Field and Bit Map

0134678951

Bit(s) Field Description

Serial Data Signals

PIPE Interface Signals

Test Signals

Registers

Altera-Defined VSEC Registers

CvP Registers

Address Range Register

Bit Name Access Description

Bits Name Access Description

PCI Express Mailbox Registers

Avalon-MM Mailbox Registers

Address Name Access

Description

Byte Offset

Sending a Write TLP

Root Port TLP Data Registers

UG-01097_avmm

100

2014.12.15

100

Related Information

101

Bits Register Description

102

Reset and Clocks

105

Hard IP for PCI Express

106

Example Design

106

Clock Domains

109

Data Rate Frequency

110

Clock Summary

112

Interrupts for Endpoints

113

MSI/MSI‑X Support

115

MsiIntfc_o[81:0]

116

MsiControl_o[15:0]

116

MsixIntfc_o[15:0]

116

IntxReq_i

116

IntxAck_o

116

Error Handling

117

Physical Layer Errors

118

Data Link Layer Errors

118

Transaction Layer Errors

119

Error Type Description

120

Status Bit Conditions

123

IP Core Architecture

125

Hard IP for PCI Express

126

Top-Level Interfaces

127

Avalon-MM Interface

127

Clocks and Reset

127

Transceiver Reconfiguration

127

Interrupts

127

Data Link Layer

128

Altera Corporation

129

Send Feedback

129

Physical Layer

130

TX Packets

131

Avalon‑MM Bridge TLPs

135

Byte Enable Value Description

136

PCI Express Avalon-MM Bridge

138

RX Block

144

Avalon-MM RX Master Block

144

TX Block

145

Interrupt Handler Block

145

Enable PLL calibration

147

Throughput Optimization

151

Throughput of Posted Writes

153

Design Implementation

155

CONF_DONE

156

Endpoint Reset

156

Root Port Reset

156

SDC Timing Constraints

157

Optional Features

159

ECRC on the RX Path

160

ECRC on the TX Path

161

Debugging

163

Setting Up Simulation

166

Use Third-Party PCIe Analyzer

168

BIOS Enumeration Issues

168

Address[31:2]

169

Figure A-6: I/O Read Request

171

7 6 5 4 3 2 1 0

175

Core Config 8 4 1

175

Additional Information

177

Date Version Changes Made

178

How to Contact Altera

182

Typographic Conventions

182

Visual Cue Meaning

183

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Altera Stratix V Avalon-MM Interface for PCIe Solutions manuels

Altera Stratix V Avalon-MM Interface for PCIe Solutions Manuel d'utilisateur (184 pages)

Table des matières

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