Altera Stratix IV GT 100G Manuel d'utilisateur télécharger pdf (Page 46)

6–24 Chapter 6: Board Test System

Using the Board Test System

Stratix IV GT 100G Development Kit User Guide October 2010 Altera Corporation

Status

These controls display current transaction performance analysis information collected

since you last clicked Start:

■ PLL lock—Shows the PLL locked or unlocked state.

■ Pattern sync—Shows the pattern synced or not synced state. The pattern is

considered synced when the start of the data sequence is detected.

■ TX and RX performance bars—Show the percentage of maximum theoretical data

rate that the requested transactions are able to achieve.

■ MBps—Shows the number of megabytes of data analyzed per second for transmit

and receive.

The QSFP Tab

The QSFP tab allows you to do loopback testing on this interface using different data

patterns, PMA settings, and clock speeds using the Clock Control application.

Figure 6–12 shows the QSFP tab.

Figure 6–12. The QSFP Tab

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Altera Stratix IV GT 100G Manuel d'utilisateur Page 46