Altera SerialLite III Streaming MegaCore Function Manuel d'utilisateur Page 31
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Figure 4-7: SerialLite III Streaming Sink Core (Advanced Clocking Mode)
Application
Module
SerialLite III Streaming Sink
Transceiver Reconfiguration Clock
SerialLite III
Streaming Link
Adaptation
Module
Transceiver Reference Clock
Core Clock
Alignment
Module
Sink User Clock
Sink User Interface
Clock Domains
Note:
1. Native PHY IP core for Arria 10 devices and Interlaken PHY IP core for Stratix V and Arria V GZ devices.
PHY IP
Core (1)
Sink Clock Generator
The clock generator is similar to the clock generator in the source core, and is only instantiated in
standard clocking mode. The clock generator synthesizes the user clock (user_clock) and core clock
(rx_coreclkin) signals from the Native PHY IP core (Arria 10 devices) or Interlaken PHY IP (Stratix V
and Arria V GZ devices) core's output clock signal. The clock generator consists of a fractional PLL and a
state machine responsible for clock generation and reset sequencing.
• For lane rates < 15.625 Gbps and all Stratix V and Arria V GZ devices, the fPLL outputs the
user_clock/user_clock_rx and rx_coreclkin based on fixed ratios determined by the SerialLite III
Streaming parameter editor.
• For 15.625 Gbps < lane rates < 17.4 Gpbs, the fPLL outputs the user_clock/user_clock_rx based on
a fixed ratio, however, the rx_coreclkin operates at the same frequency as rx_clkout.
Related Information
Source Clock Generator on page 4-4
Sink Application Module
The sink application module performs the following functions:
• Strips the Interlaken protocol bursts encapsulation from the received serial data stream and presents
the data to the user interface.
• Decodes idle control words inserted by the source application module when the data stream is not
available and mirrors the data unavailability at the source by deasserting the output valid signal at the
user interface.
The encapsulation stripping process removes burst control words that define the beginning and the end of
streaming data bursts from the data stream. This process adjusts the received data stream to repack the
data words into a contiguous sequence.
UG-01126
2015.05.04
Sink Clock Generator
4-7
SerialLite III Streaming IP Core Functional Description
Altera Corporation
Send Feedback
- Function User Guide 1
- Contents 2
- Quick Reference 4
- Item Description 5
- Continuous Mode 7
- Burst Mode 7
- Getting Started 10
- Related Information 11
- Arria 10 Designs 12
- Parameter 13
- Value Default Description 13
- File Name Description 15
- Simulating 18
- Simulation Parameters 19
- Arria 10 Simulation Testbench 21
- UG-01126 22
- 2015.05.04 22
- Altera Corporation 23
- Send Feedback 23
- Simulator File Directory 24
- Device Family 24
- Description 25
- Core Function 26
- Source Clock Generator 28
- Source Application Module 29
- Source Adaptation Module 29
- Source PPM-Absorption Module 30
- Sink Clock Generator 31
- Sink Application Module 31
- Sink Adaptation Module 32
- Lane Alignment Module 32
- Clock Domains 34
- Core Clocking 35
- Standard Clocking Mode 36
- Advanced Clocking Mode 37
- Core Latency 38
- Device Clocking Mode 39
- Parameters 39
- Latency (ns) 39
- Link-Up Sequence 40
- CRC-32 Error Injection 41
- FIFO ECC Protection 41
- User Data Interface Waveforms 41
- Signal Width 43
- Direction Description 43
- Clock Domain 47
- Guidelines 56
- Design Example Components 58
- Design Setup 59
- Design Example Operation 61
- Source Core Link Debugging 62
- Sink Core Link Debugging 64
- Error Handling 65
- Additional Information 67
- Contact Method Address 68
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