Altera Serial Digital Interface (SDI) MegaCore Function Manuel d'utilisateur Page 115
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Chapter 4: SDI Audio IP Cores 4–27
Design Example
February 2013 Altera Corporation Serial Digital Interface (SDI) MegaCore Function
User Guide
Audio Extract
The Audio Extract MegaCore function extracts the embedded AES audio from the SDI
stream. The Audio Extract MegaCore function routes the extracted AES audio to the
AES output of the daughter card.
AES Output Module
The AES output module converts the
aud_de
,
aud_ws
, and
aud_data
signals to AES
signal. This module configures the extracted internal AES audio signal,
aud_data,
without the biphase mark encoding. When this module interfaces with the Audio
Extract MegaCore function, it must use the same clock as the Audio Extract MegaCore
function.
AES Input Module
The AES input module converts the AES signal to
aud_de
,
aud_ws
, and
aud_data
(internal AES) signals to interface with Audio Embed P1. When this module interfaces
with the Audio Embed MegaCore function, both must use the same clock.
Audio Embed P0/P1
The Audio Embed P0 embeds the AES audio generated by the Audio Pattern
Generator into the video stream, as a transmitting data, for the SDI transmitter P0.
The Audio Embed P1 embeds the AES audio from the external AES input into the
video stream for the SDI duplex.
Video Pattern Generator P0/P1
You can configure the internal video pattern generator to output an SD-SDI, HD-SDI,
3G-SDI Level A or 3G-SDI Level B colorbar pattern.
Audio Pattern Generator
You can configure the internal audio pattern generator to create an AES audio test
sample that comprises an increasing count. You configure the generator using the
48-kHz clock output from the Audio Embed MegaCore function.
Ancillary Data Insertion P0/P1
The Ancillary Data Insertion module inserts the ancillary data defined by SMPTE352
into the SDI video stream.
Transceiver Dynamic Reconfiguration Control Logic
The transceiver dynamic reconfiguration control logic block handles the
reconfiguration of the receiver in the SDI duplex.
- User Guide 1
- Contents 3
- Chapter 4. SDI Audio IP Cores 4
- Appendix A. Constraints 5
- Appendix B. Clocking 5
- Features 7
- Release Information 8
- Device Family Support 8
- General Description 9
- Notes to Table 1–5: 10
- OpenCore Plus Evaluation 11
- Resource Utilization 12
- 2. Getting Started 15
- Design Flow 16
- SDI Walkthrough 17
- Parameterizing 19
- Setting Up Simulation 20
- Generating Files 20
- - SD 270 Mbps 22
- - HD 1.485 Gbps 22
- - 3G 2.97 Gbps 22
- Simulating the Design 23
- Specifying Constraints 25
- Multiple Channels 26
- Compiling the Design 28
- Programming a Device 28
- Setting Up Licensing 29
- 3. Functional Description 31
- Block Description 32
- HD-SDI LN Insertion 34
- Scrambling and NRZI Coding 35
- Transceiver Clock 35
- Receiver 36
- Word Alignment 38
- Video Timing Flags Extraction 39
- RP168 Switching Compliance 39
- HD-SDI LN Extraction 40
- HD-SDI CRC Checking 40
- Accessing Transceiver 40
- Transmitter 42
- Transmitter Clocks 42
- Receiver Clocks 43
- Notes to Table 3–5: 44
- Notes to Figure 3–8: 44
- Figure 3–9. Receiver Clocks 46
- rxdata 47
- Note to Table 3–7: 50
- Notes to Figure 3–11: 51
- Figure 3–12. Receiver Clocks 53
- New TRS reasserts 55
- Stratix IV GX 57
- Note to Table 3–10: 58
- Note to Table 3–11: 58
- Notes to Figure 3–18: 60
- Note to Figure 3–19: 61
- User Logic 62
- Encrypted SDI IP Core 62
- Cyclone IV GX 63
- Notes to Table 3–12: 70
- Note to Table 3–13: 70
- Note to Table 3–14: 71
- Note to Figure 3–30: 77
- Notes to Figure 3–33: 78
- signal in 82
- Table 3–18 on page 3–50 82
- Notes to Figure 3–40: 83
- Notes to Table 3–19: 85
- MegaCore Verification 87
- 4. SDI Audio IP Cores 89
- Functional Description 90
- Note to Table 4–4: 93
- Note to Table 4–5: 94
- MegaCore function 100
- Register Maps 103
- Parameters 105
- AES Format 109
- Avalon-ST Audio Interface 109
- Note to Figure 4–6: 110
- Instantiating the IP Cores 111
- Simulating the Testbench 112
- Design Example 113
- Components 114
- Hardware Setup 116
- D6 D7 D8 D9 D10 D11 D12 D13 118
- A. Constraints 123
- Notes to Figure A–1: 124
- (gxb_rxclk 125
- Specify Clock Characteristics 126
- Set Multicycle Paths 127
- 337.5-MHz Zero-degree Clocks 128
- Minimize Timing Skew 129
- Non Cyclone Devices 130
- Cyclone Devices Only 131
- A–10 Appendix A: Constraints 132
- B. Clocking 133
- B–2 Appendix B: Clocking 134
- C. Receive and Retransmit 135
- Loopback FIFO Buffer 136
- Additional Information 137
- Info–2 Additional Information 138
- Document Revision History 138
- How to Contact Altera 139
- Typographic Conventions 139
- Info–4 Additional Information 140
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