Altera SDI II MegaCore Manuel d'utilisateur Page 84
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Signal Width Direction Description
rx_clkout_is_
ntsc_paln
1 Input Indicates the video rate received. Applicable for all modes except
SD-SDI.
• 0 = PAL rate
• 1 = NTSC rate
rx_dataout
20 Output Parallel data out signal for the receiver.
Note: Not applicable for Arria 10 devices.
rx_dataout_valid
1 Output Data valid from the oversampling logic. The receiver asserts this
signal to indicate current data on rx_dataout is valid. The
timing (H: High, L: Low) for each video standard must have the
following settings:
• SD-SDI = 1H 4L 1H 5L
• HD-SDI = H
• 3G-SDI = H
• HD-SDI Dual Link = H
• Dual standard = SD (1H 4L 1H 5L); HD (H)
• Triple standard = SD (1H 4L 1H 5L); HD (H); 3G (H)
Note:
Not applicable for Arria 10 devices.
rx_clkout
1 Output CDR clock output signal for the hard transceiver.
rx_pll_locked
1 Output CDR PLL locked signal for the hard transceiver.
Note: Not applicable for Arria 10 devices.
rx_rst_proto_
out_b
1 Output Reset the receiver protocol downstream logic. Applicable for HD-
SDI dual link configuration only.
rx_dataout_b
20 Output Parallel data out signal for the receiver (link B). Applicable for
HD-SDI dual link configuration only.
rx_dataout_
valid_b
1 Output Data valid from the oversampling logic. The receiver asserts this
signal to indicate current data on rx_dataout_b is valid. The
timing (H: High, L: Low) for each video standard is identical to
the rx_dataout_valid signal.
rx_clkout_b
1 Output CDR clock output signal for the hard transceiver (link B).
rx_pll_locked_b
1 Output CDR PLL locked signal for the hard transceiver (link B).
Applicable for HD-SDI dual link configuration only.
Note: Not applicable for Arria 10 devices.
4-42
SDI II IP Core Signals
UG-01125
2015.05.04
Altera Corporation
SDI II IP Core Functional Description
Send Feedback
- SDI II IP Core User Guide 1
- Contents 2
- Altera Corporation 3
- Item Description 4
- SDI II IP Core Overview 6
- SMPTE372 Dual Link Support 7
- HD Dual-Link Receiver 9
- 3-GB Receiver 10
- SMPTE RP168 Switching Support 11
- Dynamic TX Clock Switching 12
- UG-01125 13
- 2015.05.04 13
- Resource Utilization 14
- Block Memory Bits 15
- Registers 15
- Secondary Logic 15
- Installation and Licensing 16
- Design Walkthrough 16
- Launching IP Catalog 17
- Parameterizing the IP Core 18
- Timing Violation 19
- Programming an FPGA Device 20
- Design Reference 20
- SDI II IP Core Parameters 21
- Parameter Value Description 22
- Design Examples 24
- Testbench 25
- Example Design 25
- Input Signal Connection 26
- Design Example 27
- Video Pattern Generator 30
- Send Feedback 30
- Related Information 31
- Interfaces 36
- Logical Channel Number 36
- Signal Width Directio 42
- Description 42
- Protocol 44
- TX PHY Management 45
- & PHY Adapter 45
- TX Protocol Transceiver 45
- Payload ID 45
- Transceiver 47
- Receiver 48
- RX Protocol 49
- RX PHY Management 49
- Management 50
- & PHY Adapter Transceiver 50
- PHY Adapter 52
- Submodules 56
- Insert/Check CRC 57
- Insert Payload ID 57
- Match TRS 59
- Scrambler 59
- TX Sample 60
- Clock Enable Generator 60
- RX Sample 61
- Step Process Description 62
- Detect Video Standard 63
- Detect 1 and 1/1.001 Rates 63
- Transceiver Controller 63
- Descrambler 64
- TRS Aligner 65
- OUTPUT DATA 66
- OUTPUT LN 66
- Sync Streams 67
- Convert SD Bits 68
- Insert Sync Bits 68
- Clocking Scheme 69
- SDI II IP Core Signals 69
- Additional Information 87
- Date Version Changes 88
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