Altera PHYLite Manuel d'utilisateur Page 23
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Feature Avalon Address R/
W
Address CSR R Control Value
Field Range
Strobe
PVT
compensat
ed input
delay
(3)
{id[3:0],
3'h2,lane_
addr[7:0],
4'hC,lgc_
sel[1:0],
3'h6,4'h0}
• lgc_sel[1:0] =
• 2'b01 for a
• 2'b10 for b
(4)
Not supported
Delay Value 9..0
Minimum Setting: 0
Maximum Setting: 1023
VCO clock periods
Incremental Delay: 1/
256th VCO clock period
Reserved 11..10
Enable 12
Reserved 31..13
Strobe
enable
phase
(3)
{id[3:0],
3'h2,lane_
addr[7:0],
4'hC,lgc_
sel[1:0],
3'h7,4'h0}
• lgc_sel[1:0]
is:
• 2'b01 for a
• 2'b10 for b
(4)
• {id[3:0],
3'h1,lane_
addr[7:0],
4'hC,
9'h194}
• {id[3:0],
3'h1,lane_
addr[7:0],
4'hC,
9'h198}
Phase Value 12..0
Minimum Setting: Refer
to Table 12
Maximum Setting: Refer
to Table 12
Incremental Delay: 1/
128th VCO clock period
Reserved 14..13
Enable 15
Reserved 31..16
Strobe
enable
delay
(3)
{id[3:0],
3'h2,lane_
addr[7:0],4'hC,
9'h008}
{id[3:0],
3'h1,lane_
addr[7:0],
4'hC,9'h1A8}
Delay Value 5..0
Minimum Setting: 0
external clock cycles
Maximum Setting: 63
external memory clock
cycles
Incremental Delay: 1
external memory clock
cycle
Reserved 14..6
Enable 15
Reserved 31..16
(3)
Modifying these values must be done on all lanes in a group.
(4)
Strobe logic b is only used by the negative pin of complementary strobes.
ug_altera_phylite
2015.01.16
Addressing
23
Altera PHYLite for Parallel Interfaces IP Core User Guide
Altera Corporation
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- Device Family Support 1
- Features 1
- Overview 2
- Related Information 3
- Clock Frequency Relationships 4
- Interface 5
- Output Path 5
- Block Description 6
- Output Path Data Alignment 7
- Input Path 8
- Path Description 9
- Legend in Figure 9 Operation 9
- Input Path Data Alignment 10
- I/O Standards 11
- 2015.01.16 12
- Input Buffer 13
- VREF Calibration Block 13
- Resistor 13
- Altera Corporation 14
- Send Feedback 14
- Calibrated VREF Settings 14
- Placement Restrictions 15
- Reference Clock 16
- Dynamic Reconfiguration 16
- Timing Components 17
- Timing Constraints and Files 17
- Timing Analysis 18
- Timing Closure Guidelines 19
- Addressing 21
- Feature Avalon Address R/ 22
- Address CSR R Control Value 22
- Field Range 22
- Address Look-Up 25
- Component Description 26
- 32-bits (4 Byte Addresses) 27
- Parameter Table Example 29
- Calibration Guidelines 31
- Parameter Settings 31
- GUI Name Values Description 32
- Read Latencies 37
- Output Path Signals 38
- Input Path Signals 40
- Example Design 42
- Generating Example Design 43
- Common Parameters 46
- Parameter Description 48
- Section Parameter Description 50
- Signal Type Description 52
- Interfaces IP Core 58
- Signal Description 59
- Document Revision History 60
- Date Version Changes 61
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