Altera Nios Development Board Stratix II Edition Manuel d'utilisateur télécharger pdf (Page 36)

2–26 Reference Manual Altera Corporation

Nios Development Board Stratix II Edition May 2007

Board Components

f For more information on the CompactFlash connector (CON3), see

www.compactflash.org and www.molex.com.

PMC Connector

(JH1 & JH2)

The PCI mezzanine card (PMC) connector, formed by JH1 and JH2,

allows Nios II systems in the FPGA to interface to daughter cards using

the standard 32-bit PMC form factor. Refer to Figure 2–11. The PMC

connector is capable of running at 33MHz or 66 MHz, and is configured

as the PMC host.

w Before connecting a daughter card to the PMC connector, the

FPGA must first be configured with a design that includes a

PMC interface. Damage to either the FPGA or daughter card can

result if the FPGA is not configured correctly.

The factory-programmed Nios II reference design does not include a

PMC interface.

H8 43 INPACK_n proto1_io39

J7 44 REG_n proto1_io40

AE7 32 CS1_n cf_cs_n

AE8 9 ATA_SEL_n cf_atasel_n

AB12 5 Power supply

enable

cf_power (2)

AB11 26 CD1_n cf_present_n

57 (U3) 41 RESET# proto1_RESET_n (3)

Notes to Ta b le 2 – 13 :

(1) Nets proto_io16, proto_io20, and proto_io21 do not connect to CON3.

(2) The FPGA I/O pin controls a power MOSFET that supplies 5.0 V V

to this net.

(3) proto1_RESET_n is driven by the EPM7256AE configuration controller device

(U3).

Table 2–13. CompactFlash Pin Table (Continued)

FPGA Pin CON3 Pin Pin Function Board Net Name (1)

1 2 ... 31 32 33 34 35 36 37 38 39 40 41 ... 61 62

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Altera Nios Development Board Stratix II Edition Manuel d'utilisateur Page 36