Altera Data Conversion HSMC Manuel d'utilisateur télécharger pdf (Page 36)

B–4 Appendix B: Pin-Out Information for the Stratix III (3SL150)

Development Board

Data Conversion HSMC Reference Manual © November 2008 Altera Corporation

60 LVDS RX or CMOS I/O bit 2 ADB_D7 HSMB_RX_P2 LVDS or 2.5 V P2

61 LVDS TX or CMOS I/O bit 2 ADA_D6 HSMB_TX_N2 LVDS or 2.5 V U6

62 LVDS RX or CMOS I/O bit 2 ADB_D6 HSMB_RX_N2 LVDS or 2.5 V R1

65 LVDS TX or CMOS I/O bit 3 ADA_D5 HSMB_TX_P3 LVDS or 2.5 V T5

66 LVDS RX or CMOS I/O bit 3 ADB_D5 HSMB_RX_P3 LVDS or 2.5 V N2

67 LVDS TX or CMOS I/O bit 3 ADA_D4 HSMB_TX_N3 LVDS or 2.5 V T4

68 LVDS RX or CMOS I/O bit 3 ADB_D4 HSMB_RX_N3 LVDS or 2.5 V P1

71 LVDS TX or CMOS I/O bit 4 ADA_D3 HSMB_TX_P4 LVDS or 2.5 V R10

72 LVDS RX or CMOS I/O bit 4 ADB_D3 HSMB_RX_P4 LVDS or 2.5 V M1

73 LVDS TX or CMOS I/O bit 4 ADA_D2 HSMB_TX_N4 LVDS or 2.5 V R9

74 LVDS RX or CMOS I/O bit 4 ADB_D2 HSMB_RX_N4 LVDS or 2.5 V N1

77 LVDS TX or CMOS I/O bit 5 ADA_D1 HSMB_TX_P5 LVDS or 2.5 V R7

78 LVDS RX or CMOS I/O bit 5 ADB_D1 HSMB_RX_P5 LVDS or 2.5 V L2

79 LVDS TX or CMOS I/O bit 5 ADA_D0 HSMB_TX_N5 LVDS or 2.5 V R6

80 LVDS RX or CMOS I/O bit 5 ADB_D0 HSMB_RX_N5 LVDS or 2.5 V L1

83 LVDS TX or CMOS I/O bit 6 ADA_OR HSMB_TX_P6 LVDS or 2.5 V N9

84 LVDS RX or CMOS I/O bit 6 ADB_OR HSMB_RX_P6 LVDS or 2.5 V K4

85 LVDS TX or CMOS I/O bit 6 ADA_OE HSMB_TX_N6 LVDS or 2.5 V N8

86 LVDS RX or CMOS I/O bit 6 ADB_OE HSMB_RX_N6 LVDS or 2.5 V K3

89 LVDS TX or CMOS I/O bit 7 ADA_SPI_CS HSMB_TX_P7 LVDS or 2.5 V M7

90 LVDS RX or CMOS I/O bit 7 ADB_SPI_CS HSMB_RX_P7 LVDS or 2.5 V J4

91 LVDS TX or CMOS I/O bit 7 AD_SDIO HSMB_TX_N7 LVDS or 2.5 V M6

92 LVDS RX or CMOS I/O bit 7 AD_SCLK HSMB_RX_N7 LVDS or 2.5 V J3

95 LVDS or CMOS clock out FPGA_CLK_A_P HSMB_CLK_OUT_P1 LVDS or 2.5 V P6

96 LVDS or CMOS clock in XT_IN_P HSMB_CLK_IN_P1 LVDS or 2.5 V N4

97 LVDS or CMOS clock out FPGA_CLK_A_N HSMB_CLK_OUT_N1 LVDS or 2.5 V P5

98 LVDS or CMOS clock in XT_IN_N HSMB_CLK_IN_N1 LVDS or 2.5 V N3

101 LVDS TX or CMOS I/O bit 8 DA13 HSMB_TX_P8 LVDS or 2.5 V L7

102 LVDS RX or CMOS I/O bit 8 DB13 HSMB_RX_P8 LVDS or 2.5 V H2

103 LVDS TX or CMOS I/O bit 8 DA12 HSMB_TX_N8 LVDS or 2.5 V L6

104 LVDS RX or CMOS I/O bit 8 DB12 HSMB_RX_N8 LVDS or 2.5 V J1

107 LVDS TX or CMOS I/O bit 9 DA11 HSMB_TX_P9 LVDS or 2.5 V L5

108 LVDS TX or CMOS I/O bit 9 DB11 HSMB_RX_P9 LVDS or 2.5 V G2

109 LVDS RX or CMOS I/O bit 9 DA10 HSMB_TX_N9

LVDS or 2.5 V L4

110 LVDS RX or CMOS I/O bit 9 DB10 HSMB_RX_N9 LVDS or 2.5 V H1

113 LVDS TX or CMOS I/O bit 10 DA9 HSMB_TX_P10 LVDS or 2.5 V K6

114 LVDS RX or CMOS I/O bit 10 DB9 HSMB_RX_P10 LVDS or 2.5 V F1

Table B–2. HSMC Port B Interface Pin-Out Information (Part 2 of 3)

Data Conversion HSMC Schematic Development Board Schematic

Board

Reference

(J1) Description

Schematic

Signal Name

Schematic

Signal Name I/O Standard

Stratix III

Number

1 2 ... 31 32 33 34 35 36 37 38 39 40 41 42 43 44

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Altera Data Conversion HSMC Manuel d'utilisateur Page 36

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