Altera Cyclone V GX FPGA Development Board Manuel d'utilisateur Page 49
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Chapter 2: Board Components 2–41
Memory
May 2013 Altera Corporation Cyclone V GX FPGA Development Board
Reference Manual
K2
DDR3B_A3
W29 1.5-V SSTL Class I Address bus
L8
DDR3B_A4
U23 1.5-V SSTL Class I Address bus
L2
DDR3B_A5
AA30 1.5-V SSTL Class I Address bus
M8
DDR3B_A6
R23 1.5-V SSTL Class I Address bus
M2
DDR3B_A7
AC30 1.5-V SSTL Class I Address bus
N8
DDR3B_A8
T23 1.5-V SSTL Class I Address bus
M3
DDR3B_A9
AB29 1.5-V SSTL Class I Address bus
H7
DDR3B_A10
R30 1.5-V SSTL Class I Address bus
M7
DDR3B_A11
R26 1.5-V SSTL Class I Address bus
K7
DDR3B_A12
T25 1.5-V SSTL Class I Address bus
N3
DDR3B_A13
AD29 1.5-V SSTL Class I Address bus
J2
DDR3B_BA0
W30 1.5-V SSTL Class I Bank address bus
K8
DDR3B_BA1
T24 1.5-V SSTL Class I Bank address bus
J3
DDR3B_BA2
V30 1.5-V SSTL Class I Bank address bus
G3
DDR3B_CASN
T30 1.5-V SSTL Class I Row address select
G9
DDR3B_CKE
L28 1.5-V SSTL Class I Column address select
G7
DDR3B_CLK_N
P22 1.5-V SSTL Class I Differential output clock
F7
DDR3B_CLK_P
P23 1.5-V SSTL Class I Differential output clock
H2
DDR3B_CSN
U29 1.5-V SSTL Class I Chip select
B7
DDR3B_DM4
P29 1.5-V SSTL Class I Write mask byte lane
B3
DDR3B_DQ32
P28 1.5-V SSTL Class I Data bus byte lane 4
C7
DDR3B_DQ33
K28 1.5-V SSTL Class I Data bus byte lane 4
C2
DDR3B_DQ34
M27 1.5-V SSTL Class I Data bus byte lane 4
C8
DDR3B_DQ35
P30 1.5-V SSTL Class I Data bus byte lane 4
E3
DDR3B_DQ36
N29 1.5-V SSTL Class I Data bus byte lane 4
E8
DDR3B_DQ37
M29 1.5-V SSTL Class I Data bus byte lane 4
D2
DDR3B_DQ38
R27 1.5-V SSTL Class I Data bus byte lane 4
E7
DDR3B_DQ39
N30 1.5-V SSTL Class I Data bus byte lane 4
D3
DDR3B_DQS_N4
R25
Differential 1.5-V SSTL
Class I
Data strobe P byte lane 4
C3
DDR3B_DQS_P4
P25
Differential 1.5-V SSTL
Class I
Data strobe N byte lane 4
G1
DDR3B_ODT
V29 1.5-V SSTL Class I On-die termination enable
F3
DDR3B_RASN
T29 1.5-V SSTL Class I Row address select
N2
DDR3B_RESETN
AB27 1.5-V SSTL Class I Reset
H3
DDR3B_WEN
T28 1.5-V SSTL Class I Write enable
H8
DDR3B_ZQ05
— 1.5-V SSTL Class I ZQ impedance calibration
Table 2–30. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)
Board Reference
Schematic
Signal Name
Cyclone V GX
Pin Number
I/O Standard Description
- Reference Manual 1
- Contents 3
- Additional Information 4
- 1. Overview 5
- Board Component Blocks 6
- Chapter 1: Overview 1–3 7
- Handling the Board 8
- 2. Board Components 9
- Board Overview 10
- I/O Resources 13
- FPGA Configuration 18
- Figure 2–3. JTAG Chain 19
- Note to Table 2–6: 21
- Figure 2–4. PFL Configuration 22
- Status Elements 23
- Setup Elements 24
- CPU Reset Push Button 25
- MAX V Reset Push Button 25
- Program Select Push Button 25
- Clock Circuitry 26
- Off-Board Clock Input/Output 27
- General User Input/Output 28
- General LEDs 29
- HSMC LEDs 29
- PCI Express LEDs 30
- Debug Header 31
- Components and Interfaces 32
- 10/100/1000 Ethernet 34
- SDI Video Output/Input 39
- DDR3 SDRAM 41
- Synchronous SRAM 50
- Power Supply 53
- Power Distribution System 54
- Power Measurement 55
- Notes to Table 2–35: 56
- 3. Board Components Reference 57
- Note to Table: 59
- Typographic Conventions 60
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