Altera Cyclone III LS FPGA Development Board Manuel d'utilisateur Page 5

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© October 2009 Altera Corporation Cyclone III LS FPGA Development Board Reference Manual
1. Overview
Introduction
This document describes the hardware features of the Cyclone
®
III LS FPGA
development board, including the detailed pin-out and component reference
information required to create custom FPGA designs that interface with all
components of the board.
General Description
The Cyclone III LS FPGA development board provides a hardware platform for
developing and prototyping low-power, secure, high-volume, feature-rich designs as
well as to demonstrate the Cyclone III LS device's on-chip memory, embedded
multipliers, and the Nios
®
II embedded soft processor. The board provides a wide
range of peripherals and memory interfaces to facilitate the development of the
Cyclone III LS FPGA designs.
Two high-speed mezzanine card (HSMC) connectors are available to add additional
functionality via a variety of HSMCs available from Altera
®
and various partners.
f To see a list of the latest HSMCs available or to download a copy of the HSMC
specification, refer to the Development Board Daughtercards page of the Altera
website (www.altera.com).
The Cyclone III LS FPGAs are the first to offer a suite of security features at the silicon,
software, and intellectual property (IP) level on a low-power, high-functionality
FPGA. This suite of security features protects your IP from tampering, reverse
engineering, and cloning. Additionally, these devices enable you to introduce
redundancy in a single chip using design separation, which in turn reduces the size,
weight, and power of your applications.
The Cyclone III LS FPGA development board is especially suitable for low-power,
secure, logic-rich applications that require stringent signal and power integrity
solutions.
f For more information on the following topics, refer to the respective documents:
Cyclone III device family, refer to the Cyclone III Device Handbook.
Cyclone III LS security features, refer to the Partitioning FPGA Designs for
Redundancy and Information Security Webcast page of the Altera website.
HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification.
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