Altera Cyclone II DSP Development Board Manuel d'utilisateur Page 74
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2–66 Reference Manual Altera Corporation
Cyclone II DSP Development Board August 2006
Power Supply
On-Board Power Regulators (U2, U7, U8, U9, U10, U23 & U24)
There are seven voltage regulators on the Cyclone II DSP development
board to control eight separate voltage rails. Two switching regulators
provide 3.3 V, 1.8 V, and 6 V. Five linear regulators provide 5 V, 1.2 V,
0.9 V, VCCA_DAC, and VCCA_ADC. Table 2–35 describes each voltage
regulator. See Figure 2–24 for the locations of the voltage regulators on
the Cyclone II DSP development board.
Table 2–35. Cyclone II DSP Development Board Regulators
Board
Reference
Type
Voltage
Output
Provides Power To Manufacturer Part Number
U2
Dual
output
switching
regulator
3.3 V
● Cyclone II VCCIO banks 1, 2, 5, and 6
● Clock oscillators and buffers
● Expansion Prototype Connector
● SSRAM
● EPCS64
● LEDs and seven-segment displays
● DIP switches and push-buttons
● Audio CODEC
● Video DAC
Texas
Instruments
TPS51020
1.8 V
● DDR2 SDRAM DIMM
● Cyclone II VCCIO banks 3, 4, 7, and 8
TPS51020
U7
Linear
regulator
1.2 V ● Cyclone II VCCINT
● VCCA_PLL
● VCCD_PLL
UC382TD
U8
Linear
regulator
0.9 V ● DDR2 SDRAM VTT TPS51100
U9
Switching
regulator
6V ● VCCA_ADC regulator
● VCCA_DAC regulator
TPS40055
U10
Linear
regulator
5V ● Linear 0.9V regulator
● Expansion Prototype Connector card
voltage limiters
REG104GA
U23
Linear
regulator
3.3 V
5V
● D/A Converter voltage REG104GA
U24
Linear
regulator
3.3 V ● A/D Converter voltage REG104GA
- Reference Manual 1
- MNL-CII012805-1.1 2
- Contents 3
- About This Manual 5
- Typographic 6
- Conventions 6
- Chapter 1. Introduction 7
- Features Overview 8
- Chapter 2. Cyclone II DSP 9
- Development 9
- Board Components 9
- Components & Interfaces 10
- USER EPCS (U36) 11
- (Flash Memory) 11
- Expansion Connectors 13
- General Connectors 13
- DIMM_SYNC_CLK) is a 14
- CONFIG_DONEn is asserted) 15
- Featured Device 17
- User Interfaces 17
- Closed Position 19
- Open Position 19
- USER_PB3 AE14 20
- USER_PB2 AE22 20
- USER_PB1 AE16 20
- USER_PB0 AC18 20
- Audio CODEC Converter (U11) 22
- Audio Jacks (J10, J14, J16) 22
- VGA Output Connector (J21) 23
- D/A Converter (U25 & U30) 25
- D/A Converter Clocks 26
- CLK_OSC_DACA (Channel A) 27
- CLK_OSC_DACB (Channel B) 27
- FPGA_TO_DAC_CLK 27
- SMA_TO_DAC_CLK 27
- Note to Table 2–13: 28
- A/D Converter (U26 & U31) 30
- A/D Converter Clocks 31
- CLK_OSC_ADCA (Channel A) 32
- CLK_OSC_ADCB (Channel B) 32
- FPGA_TO_ADC_CLK 32
- SMA_TO_ADC_CLK 32
- Note to Table 2–18: 33
- Components 34
- DDR2 SDRAM DIMM Clocks 35
- Memory Components 36
- Note to Figure 2–12: 36
- EPCS Select (J29) 45
- Synchronous SRAM Device (U22) 47
- Note to Table 2–23: 49
- ■ EVM_CEn2 selects the SSRAM 50
- J15Pin 1 51
- Pin 1 Pin 1 51
- Notes to Figure 2–16: 52
- Note to Table 2–24: 55
- General 58
- Connectors 58
- Mictor Connector (J12) 61
- Notes to Figure 2–19: 62
- Note to Table 2–28: 64
- Status LEDs & 65
- Reset/Power 65
- Switches 65
- USER RESET 66
- SYS RESET 66
- Clock Circuitry 67
- Setting the Clocks 68
- CLK SMA Connector (J17) 69
- Clock Buffer (U16) 71
- Power Supply 72
- Power Plane 78
- Supplies 78
- Settings 78
- Appendix A. DDR2 SDRAM 79
- DIMM Connector Pin Out Table 79
- DIMM_DQS5 C12 C12 82
- DIMM_DQS6 B14 B14 82
- DIMM_DQS7 C17 C17 82
- DIMM_DQS8 B6 B6 82
- Appendix B. SSRAM 83
- Pin-Out Table 83
- Note to Ta ble B –1: 85
- Appendix C. Cyclone II EP2C70 87
- Device Pin-Out Table 87
- Appendix D. Restoring the 109
- Factory Design 109
- SAFE/USER Mode 110
- ASI Connector 111
- JTAG Cable 111
- Introduction 112
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