Altera Clock Control Block IP Core Manuel d'utilisateur Page 10
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
2–4 Chapter 2: Parameter Settings
MegaWizard Parameter Settings
Clock Control Block (ALTCLKCTRL) Megafunction February 2014 Altera Corporation
User Guide
6 Summary Page
Specify the types of files to be generated. Only the files
marked with red check marks are optional.
Choose from the following types of files:
■ Variation file
(4)
■ AHDL Include file (<function name>.inc)
■ VHDL component declaration file
(<function name>.cmp)
■ Quartus II symbol file (<function name>.bsf)
■ Instantiation template file (<function name>_inst.v)
■ Verilog HDL black box file (<function name>_bb.v)
■ Synthesis area and timing estimation netlist
(_syn.v)
(5)
For more information about the wizard-generated files,
refer to Quartus II Help or to the Recommended HDL
Coding Styles chapter in volume 1 of the Quartus II
Handbook.
Notes to Table 2–1:
(1) This option is not supported in Cyclone III devices.
(2) You can change the number of clock inputs only if you choose the Auto or For global clock options.
(3) Not supported if you choose the For periphery clock option.
(4) The Variation file contains wrapper code in the language you specified on page 2a and is automatically generated.
(5) The synthesis area and timing estimation netlist file (_syn.v) is automatically generated if the Generate netlist option on page 4 is turned on.
(6) This mode is not supported in Arria 10 devices.
Table 2–1. ALTCLKCTRL MegaWizard Plug-In Manager Page Options and Description (Part 4 of 4)
MegaWizard
Plug-in
Manager
Page
Configuration Setting Description
- User Guide 1
- Contents 3
- 1. About this Megafunction 5
- Device Support 6
- 2. Parameter Settings 7
- MegaWizard Parameter Settings 8
- Notes to Table 2–1: 10
- 3. Functional Description 13
- Global Clock Control Block 14
- Regional Clock Control Block 15
- Clock Enable Signals 16
- Connectivity Restrictions 17
- Input Ports 19
- Output Ports 19
- Verilog HDL Prototype 20
- VHDL Component Declaration 20
- VHDL LIBRARY-USE Declaration 21
- Additional Information 23
- How to Contact Altera 24
- Typographic Conventions 25
- Info–4 Additional Information 26
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