Altera Advanced SEU Detection IP Core Manuel d'utilisateur télécharger pdf (Page 19)

The .smh contains a mask for design sensitive bits in a compressed format. The sensitivity mask is

generated for the entire design. Hierarchy tagging provides the following benefits:

• Hierarchy tagging provides the following benefits:

• Increases system stability by avoiding disruptive recovery procedures for inconsequential errors.

• Allows diverse corrective action for different design logic.

Using Partitions to Specify Logic Sensitivity ID

In the Quartus II software, you can designate a design block as a design partition. You can then assign a

sensitivity value to the partition.

The PARTITION_ASD_REGION_ID global assignment specifies the numeric value from 0 to 16. The value

represents the sensitivity tag associated with this partition:

set_global_assignment -name PARTITION_ASD_REGION_ID <asd_id> -section_id

<partition_name>

A sensitivity tag of 1 is the same as no PARTITION_ASD_REGION_ID assignment, specifying basic sensitivity

level: "region used in design". If a soft error occurs in this partition, the error is reported back as a critical

error in the sensitivity region 1.

A sensitivity tag of 0 is reserved, as indication that CRAM bits are not used in your design. You can

explicitly set it to indicate that partition is not-critical, and force the partition to be completely excluded

from the sensitivity mapping.

Note:

You can create multiple partitions with the same sensitivity tag in a design.

Design Partitions Properties

Specify the sensitivity ID assigned to the partition in the ASD Region column in the Design Partition

window.

Figure 12: ASD Region Column in the Design Partition Window

Sensitivity Map Header File Lookup

The .smh contains critical bit information about the design. The sensitivity data is generated as a standard

Intel hex (big-endian) .smh file during .sof generation.

ALTADVSEU

2015.05.04

Using Partitions to Specify Logic Sensitivity ID

Altera Advanced SEU Detection IP Core User Guide

Altera Corporation

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Altera Advanced SEU Detection IP Core Manuel d'utilisateur Page 19