Altera Active Serial Memory Interface Manuel d'utilisateur Page 34

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Figure 18: Execution of 4BYTEADDREN For Enabling 4-byte Addressing Mode
This figure shows an example of the latency when the Altera ASMI Parallel IP core is performing the 4-
byte addressing operation. This figure does not reflect the true processing time.
4-byte Addressing Exit Operation for an EPCQ256/EPCQ-L256 or Larger Devices
The ex4b_addr input port allow you to exit the 4-byte addressing operation. These input ports are
available when you use an EPCQ256/EPCQ-L256 or larger devices.
Note: The 4-byte addressing exit operation is supported for EPCQ256/EPCQ-L256 or larger devices only,
so you must enable 4-byte addressing when you use an EPCQ256/EPCQ-L256 or larger devices.
To exit 4-byte addressing mode, pull the wren signal high, followed by at least one clock cycle. If wren
signal is zero, the 4-byte addressing mode exit operation will not be carried out even though the
ex4b_addr is high. After the IP core receives the command, the IP core asserts the busy signal to indicate
that the exit operation is in progress.
Document Revision History
The following table lists the revision history for this document.
Date Version Changes
December 2014 2014.12.15
Added EPCQ-L devices.
Added sce[] port and definition.
Added die_erase parameter.
Updated diagrams to reflect newly added port and parameter.
July 2014 2014.07.18
Replaced MegaWizard Plug-In Manager information with IP Catalog.
Added standard information about upgrading IP cores.
Added standard installation and licensing information.
Renamed ALTASMI_PARALLEL megafunction to Altera ASMI
Parallel IP core.
December 2013 4.2 Updated the following sections to include ex4b_addr information:
“Parameter Settings” on page 2–2.
“Input Ports” on page 2–8.
“ALTASMI_PARALLEL Block Diagram” on page 2–1.
Added “4-byte Addressing Exit Operation for an EPCQ256 Device” on
page 3–17.
34
4-byte Addressing Exit Operation for an EPCQ256/EPCQ-L256 or Larger Devices
UG-ALT1005
2014.12.15
Altera Corporation
Altera ASMI Parallel IP Core User Guide
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