Altera PHYLite Manuel d'utilisateur

Altera PHYLite for Parallel Interfaces IP Core UserGuide2015.01.16ug_altera_phyliteSubscribeSend FeedbackThe Altera PHYLite for Parallel Interfaces IP

Legend in Figure 9 Operation4 The strobe is optionally delayed to create a phase offset between the strobe and theinput data (for example, 90° phase s

Figure 12: Example Input (Quarter Rate DDR) - UnalignedI/O StandardsThe Altera PHYLite for Parallel Interfaces IP core allows you to set I/O standards

I/O Standard Valid InputTerminations (Ω) (1)Valid OutputTerminations(Ω)(1)RZQ(Ω)Differential/Complementary I/OSupport1.2-V POD 34, 40, 48, 60, 80,120,

Figure 13: VREFInput Buffer+-VrefRRVCCNInternal VREF6 bits binary weighted resistors dividor6 bits Static VREF Code6 bits calibrated VREF code from Av

avl_writedata[5:0] % of VCCN000101 63.20%000110 63.84%000111 64.48%001000 65.12%001001 65.76%001010 66.40%001011 67.04%001100 67.68%001101 68.32%00111

avl_writedata[5:0] % of VCCN100100 83.04%100101 83.68%100110 84.32%100111 84.96%101000 85.60%101001 86.24%101010 86.88%101011 87.52%101100 88.16%10110

Related Information• Device Pin-Out FileFor specific DQS group numbers refer to the specific device Pin-Out fileReference ClockThe reference clock mus

Timing ComponentsTable 9: Timing ComponentsCircuit Category TimingPathsSource Destination DescriptionSource Synchronousand optionallycalibrated (2)Rea

<variation_name>.sdcYou can find the location of the <variation_name>.sdc file in the .qip, which is generated during the IPgeneration. Th

Location DescriptionFPGA The Altera PHYLite for Parallel Interfaces IP core generation creates the clock settings for theuser core clock and the perip

OverviewThe Arria 10 I/O subsystem is located in the I/O columns. Each column consists of up to 13 I/O banksand one I/O aux.Figure 1: I/O Column for A

Related InformationDynamic Reconfiguration on page 20For more information about using the dynamic reconfiguration feature to calibrate the I/O pathInt

Figure 14: Logical RTL View to Physical Column PlacementThis figure shows an example of a daisy chain consisting of the Arria 10 External Memory Inter

Table 11: Address MapFeature Avalon Address R/WAddress CSR R Control ValueField RangePin OutputPhase{id[3:0],3'h2,lane_addr[7:0],pin{4:0],8'

Feature Avalon Address R/WAddress CSR R Control ValueField RangeStrobePVTcompensated inputdelay (3){id[3:0],3'h2,lane_addr[7:0],4'hC,lgc_sel

Feature Avalon Address R/WAddress CSR R Control ValueField RangeRead validdelay (3){id[3:0],3'h2,lane_addr[7:0],4'hC,9'h00C}{id[3:0],3&

VCO MultiplicationFactorCore RateMinimum InterpolatorPhaseMaximum Interpolator Phase2Full 0x180 0xFFFHalf 0x100 0xFFFQuarter 0x380 0xFFF4Full 0x200 0x

Figure 15: Lane and Pin Placement Dependent AddressesThis figure shows an example of a placed group with two lanes, 16 data pins and a differential st

Figure 16: Memory OverviewGroup 0 Pin 1 Group 0 Pin 0num_lanes[1:0],num_pins[5:0]Needed for pin address lookupsNeeded for simplifying strobe feature l

Legend in Figure 16 Description2 Retrieve number of groups in the interface (cache once per interface)• {id[3:0],24'h00E000} + {4'h0,pt_ptr[

Parameter Table ExampleFigure 17: Parameter Table ExampleThis figure shows an example of a design containing two Altera PHYLite interfaces, each with

Figure 2: 48-I/O Banks in Arria 10 DevicesThis figure shows a detailed view of the I/O bank in Arria 10 devices.2L2K2J2I2H2G2F2A3H3G3F3E3D3C3B3ATransc

Figure 18: Avalon ControllerThe input interface is as follows:avl_in_address[31:0] ={8'h00,interface_id[3:0],grp[4:0],pin[5:0],csr[0],register[7:

Register[7:0] Pin[5:0] Csr[0] AvalonR/WCSR R/W R/W Data on avl_readdata/avl_writedataAVL_CTRL_REG_DQS_EN_DELAY0 R: 0/1W: 0R/W R {26'h0000000,dqs_

GUI Name Values DescriptionGeneral Tab- these parameters are set on a per interface basisClocksMemory clock frequency 100 MHz - 1333.333MHzExternal me

GUI Name Values DescriptionDesired Frequency — Specifies the output clock frequency of thecorresponding output clock port, outclk[], inMHz. The defaul

GUI Name Values DescriptionI/O standardSSTL-12SSTL-125SSTL-135SSTL-15SSTL-15 Class ISSTL-15 Class IISSTL-18 Class ISSTL-18 Class II1.2-V-HSTL Class I1

GUI Name Values DescriptionRead latency 1 to 63 externalinterface clock cyclesExpected read latency of the external device inmemory clock cycles. The

GUI Name Values DescriptionUse separate strobes —Separate the bidirectional strobe into input andoutput strobe pins. Using separate strobes is onlyava

Read LatenciesTable 17: Read LatenciesThis table list the read latencies.VCO FrequencyMultiplicationFactorCore Clock Rate SettingFull-Rate Half-Rate Q

Output Path SignalsTable 19: Output Path SignalsOutput path signals are signals that are available when you set the Pin Type parameter to either Outpu

Signal Name Direction Width Descriptiondata_out_n/data_io_nOutput/Bidirectional1 to 24 Negative data output from pinenabled when data configura‐tion i

Clock Domain DescriptionCore clock This clock is generated internally by the IP core and output to the core to be used forall transfers between the FP

Input Path SignalsTable 20: Input Path SignalsInput path signals are signals that are available when you set the Pin Type parameter to Input or Bidire

Signal Name Direction Width Descriptionstrobe_in/strobe_ioInput/Bidirectional1Positive strobe from pin. If the pintype is set to Input, the strobe_ins

Signal Name Direction Width Descriptionavl_readdata_valid Output 1 Indicates that read data has returned.avl_waitrequest Output 1 Stalls upstream logi

Generating Example DesignYou can generate a example design by clicking Example Design in the IP Parameter Editor.The software generates a user defined

Figure 19: High-Level View of the Simulation Example Design with One GroupThis figure shows a high-level view of the simulation example design with on

Therefore, when migrating from the ALTDQ_DQS2 IP core to the Altera PHYLite for Parallel InterfacesIP core, you must:• Configure the Altera PHYLite fo

Figure 21: ALTDQ_DQS2 IP Core Parameter for Stratix V DevicesCommon ParametersTable 23: Common ParametersThis table lists the common parameters for th

ALTDQ_DQS2 IP core Altera PHYLite for Parallel Interfaces IP coreDifferential/Complementary output strobeNote: Supports single, complementary, anddiff

Figure 23: Additional Parameter in Group TabTable 24: Additional Parameters in the Altera PHYLite for Parallel Interfaces IP CoreParameter Description

Parameters for ALTDQ_DQS2 IP Core OnlyThe following figures and table show the parameters supported in the ALTDQ_DQS2 IP core but not inAltera PHYLite

InterfaceFigure 4: Top-Level InterfaceThis figure shows the top-level diagram of the Altera PHYLite for Parallel Interfaces IP core interface.PLLI/O L

Table 25: ALTDQ_DQS2 IP Core Specific ParametersSection Parameter DescriptionGeneral SettingsExtra output-only pins This option is commonly used as da

Section Parameter DescriptionCapture StrobeUse capture strobe enable blockYou cannot access the capture strobe in theAltera PHYLite for Parallel Inter

To begin, follow these steps:1. In the Quartus II software version 14.0a10, open the nand_flash_example_14.0a10.qar.2. In the Quartus II dialog box, c

Synchronous Signals DescriptionCMD/ADDR signals (outputfrom FPGA, input to memory)Signal Type DescriptionALE Input Address latch enable. Loads an addr

Figure 27: ALTDQ_DQS2 Settings for Bidirectional Type DQ and DQSNote: The DQS enable block must be enabled for NAND Flash, which has bidirectional str

The following figure shows the RTL viewer for a NAND Flash simple design based on the ALTDQ_DQS2IP core from this implementation.Figure 29: RTL viewer

Figure 30: General Tab SettingsFigure 31: Group 0 settings (Bidirectional type for DQ and DQS)56Implementation using the Altera PHYLite for Parallel I

Figure 32: Group 1 settings (Output type for Addr/Cmd)Figure 33: Group 2 settings (Input type for the Ready signal)The following figure shows the RTL

Figure 34: RTL Viewer for a NAND Flash Simple Design Based on the Altera PHYLite for ParallelInterfaces IP Core58Implementation using the Altera PHYLi

Manual Migration between ALTDQ_DQS2 and Altera PHYLite for Parallel Interfaces IP CoresFigure 35: Migration Process Overview for the NAND Flash Simple

Figure 5: Output PathThis figure shows the output path for the Altera PHYLite for Parallel Interfaces IP core.Write FIFOdata_io data_outoe_outoct_outI

Table 27: Connecting Similar or New SignalsSignal Descriptionrdata_en In the Altera PHYLite for Parallel Interfaces IP core, this signal is similar bu

Date Version ChangesDecember,20142014.12.30• Updated the name of the IP core from Altera PHYLite forMemory to Altera PHYLite for Parallel Interfaces.•

Figure 6: Output Path - Write Latency 0These figures show the waveform diagrams for the output path.Figure 7: Output Path - Write Latency 3Related Inf

Figure 8: Example Output for Quarter Rate DDRRelated Information• External Memory Interface HandbookFor more information about the AFI 3.0 specificati

Table 3: Blocks in Data, Strobe, and Read Enable PathsThis table lists the information about these paths.Path DescriptionData Path Consists of a PVT c