Altera PHYLite Manuel d'utilisateur Page 58
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- Table des matières
- MARQUE LIVRES
- Device Family Support 1
- Features 1
- Overview 2
- Related Information 3
- Clock Frequency Relationships 4
- Interface 5
- Output Path 5
- Block Description 6
- Output Path Data Alignment 7
- Input Path 8
- Path Description 9
- Legend in Figure 9 Operation 9
- Input Path Data Alignment 10
- I/O Standards 11
- 2015.01.16 12
- Input Buffer 13
- VREF Calibration Block 13
- Resistor 13
- Altera Corporation 14
- Send Feedback 14
- Calibrated VREF Settings 14
- Placement Restrictions 15
- Reference Clock 16
- Dynamic Reconfiguration 16
- Timing Components 17
- Timing Constraints and Files 17
- Timing Analysis 18
- Timing Closure Guidelines 19
- Addressing 21
- Feature Avalon Address R/ 22
- Address CSR R Control Value 22
- Field Range 22
- Address Look-Up 25
- Component Description 26
- 32-bits (4 Byte Addresses) 27
- Parameter Table Example 29
- Calibration Guidelines 31
- Parameter Settings 31
- GUI Name Values Description 32
- Read Latencies 37
- Output Path Signals 38
- Input Path Signals 40
- Example Design 42
- Generating Example Design 43
- Common Parameters 46
- Parameter Description 48
- Section Parameter Description 50
- Signal Type Description 52
- Interfaces IP Core 58
- Signal Description 59
- Document Revision History 60
- Date Version Changes 61
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