
Related Information
RXFIFO Address Width on page 9-2
Information about programming the depth of the Reassembly FIFO with the RXFIFO_ADDR_WIDTH
parameter.
50G Interlaken IP Core Management Interface
The 50G Interlaken IP core management interface allows you to communicate with IP core internal status
and control registers. This interface manages the PMA (resets and serial loopback controls) and PCS
control and status registers. This interface does not provide access to the hard PCS registers on the device.
The management interface is a typical 32-bit memory-mapped register port. It complies with the Avalon
Memory-Mapped (Avalon-MM) specification defined in the Avalon Interface Specifications.
Table 5-5: 50G Interlaken IP Core Management Interface Signals
Signal Name Direction Width
(Bits)
Description
50G Interlaken IP Core Management Interface Signals
mm_clk Input 1 Management clock. Clocks the register accesses. It is
also used for clock rate monitoring and some analog
calibration procedures. You must run this clock at a
frequency in the range of 100 MHz–125 MHz.
mm_clk_locked Input 1 Assert this signal to indicate that mm_clk is stable.
The IP core responds to this signal in the same way it
responds to the reset_n signal: loss of lock restarts
the reset sequence.
Altera recommends that you tie this signal high and
not rely on its functionality. It is expected to be
deprecated in the near future.
mm_read Input 1 Read access to the register ports.
mm_write Input 1 Write access to the register ports.
mm_addr Input 16 Address to access the register ports.
mm_rdata Output 32 When mm_rdata_valid is high, mm_rdata holds valid
read data.
mm_rdata_valid Output 1 Valid signal for mm_rdata.
mm_wdata Input 32 When mm_write is high, mm_wdata holds valid write
data.
5-12
50G Interlaken IP Core Management Interface
UG-01140
2015.05.04
Altera Corporation
50G Interlaken MegaCore Function Signals
Send Feedback
Commentaires sur ces manuels