Altera Partial Reconfiguration IP Core Manuel d'utilisateur

Partial Reconfiguration IP Core2015.05.04UG-PARTRECONSubscribeSend FeedbackPartial reconfiguration (PR) is fully supported in the Stratix® V device fa

Port Name Width Direction Functionstatus[2..0]3Output A 3-bit error output used toindicate the status of PR event.Once an error is detected (PR_ERROR,

Port Name Width Direction Functiondouble_pr1Input When the pr_start signal istriggered until the de-assertionof freeze signal, a signalasserted high o

Port Name Width Direction Functionavmm_slave_write 1Input Avalon-MM write control.This signal is ignored duringJTAG debug operations.avmm_slave_writed

Port Name Width Direction Functionpr_done_pin1Input Available when the PR IP core isused as the External Host.Connect this port to thededicated PR_DON

1. Avalon Memory Mapped Master component writes 16’h0001 (or 16’h0003 if the design requiresdouble PR) to this IP address offset 0x1 to trigger PR ope

Table 7: PR_CSR Control and Status RegistersBit Offset Description0Read and write control register for pr_start signal.Refer to “Input/output Port Lis

Partial Reconfiguration IP Core Timing SpecificationThis timing diagram illustrates a successful Partial Reconfiguration IP core operation. Pass or fa

Related Informationlink/nik1412467993397/nik1412467975241Avalon Interface Specifications for data transfer with backpressureAvalon Memory Map Slave In

The controller receives data and sends it to the prblock WYSIWYG atom primitive during a PR eventwith the clock-to-data ratio (CDRATIO) you specify wh

The PR data interface provides you with selectable input data width; x1, x2, x4, x8, x16, and x32. It can beconnected to ASMI_PARALLEL as well as the

Figure 2: Managing Partial Reconfiguration with an Internal or External HostThe figure shows how these blocks should be connected to the PR control bl

Figure 7: Adding PR Programming File2. After adding thePR bitstream, you can change or delete the Partial Reconfiguration programming fileby clicking

Figure 8: Change PR Programming File or Delete PR Programming File3. Click Start to configure the PR bitstream. The Quartus II Programmer generates an

Figure 9: Starting PR Bitstream Configuration4. Configure the valid .rbf in JTAG debug mode with the Quartus II Programmer.22Configuring Partial Recon

Figure 10: Configuring Valid .rbf5. The JTAG debug mode is also supported if the PR IP core is pre-programmed on the specified device.UG-PARTRECON2015

Figure 11: Partial Reconfiguration IP Core Successfully Pre-programmed6. The Quartus II Programmer reports error when you try to configure the corrupt

Figure 12: Configuring Corrupted .rbfSample Freeze Wrapper for Multiple PR RegionsThe following Verilog HDL pseudocode shows an example of how to crea

my_freeze_region_A ( .freeze(freeze_A_w), … ); // Freeze wrapper for input signals of single PR region B // Follow existing recommendation

Related InformationDesign Planning for Partial ReconfigurationFor more information on instantiating the an external host for partial reconfigura

Figure 3: Partial Reconfiguration IP Core in the Qsys Interface4. Turn on Enable Avalon-MM slave interface to use the Avalon Memory Map Slave interfac

design. You can instantiate the PR IP core as the external host on any supported Altera devices asspecified in the user selectable device family list.

7. Click Exit.Related Information• Instantiating the Partial Reconfiguration IP Core in the Qsys Interface on page 2• Partial Reconfiguration IP Core

When Enable bitstream compatibility check is turned on, the PR IP core creates a PR bitstream ID anddisplays it in the configuration dialog box.Relate

IP Core Option Value Default DescriptionPR bitstream ID -2147483648 to21474836470 Specifies a signed 32-bit integervalue of the PR bitstream ID forExt

Partial Reconfiguration IP Core PortsI/O Port List for PR IP CoreTable 1: Clock/Reset PortsThese options are always available.Port Name Width Directio

Table 3: Conduit InterfaceThese options are available when Enable Avalon-MM slave interface parameter is turned Off.Port Name Width Direction Function