Altera Double Data Rate I/O Manuel d'utilisateur

Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT,and ALTDDIO_BIDIR) IP Cores User Guide2015.01.23UG-DDRMGAFCTNSubscribeSend FeedbackThe Altera®® DDR I/O

(dataout_h and dataout_l) can be disabled. These features are especially useful for generating datastrobes like DQS.Figure 5: Bidirectional DDR I/O Pa

• Implementing Double Data Rate I/O Signaling in Cyclone DevicesFor more information about the DDR registers in Cyclone devicesDDR I/O TimingThis figu

Design Example 2: 8-Bit DDR Divider Using ALTDDIO_BIDIRThis section presents a design example that uses the ALTDDIO_BIDIR IP core to generate a divide

ParameterEditor PageParameter Value3Currently selected device family Stratix IVMatch project/default Turned onWidth: (bits) 8Use ‘aclr’ port Turned of

Related InformationDesign Example 2: 8-Bit DDR Divider Using ALTDDIO_BIDIRCreate the LPM_DIVIDE ModuleFollow these steps to create the lpm_divide modu

Parameter Editor Page Parameter Value4Do you want to pipelinethe function?Select Yes, I want an output latencyof 1 clock cycleCreate an AsynchronousCl

This design implements the same divider as that in Design Example 1, but the functionality of theALTDDIO_IN and ALTDDIO_OUT modules is implemented in

Figure 8: ModelSim Simulation ResultsThis figure shows the expected simulation results in ModelSim-Altera software.Related InformationDivider Design i

NameRequiredDescriptionsset No Synchronous set input. The sclr and sset ports cannot be connected at thesame time. The sset port is available for Arri

Name Required Descriptionoe No Output enable for the dataout port. Active-highsignal. You can add an inverter if you need an active-low oe.sclr No Syn

The DDR registers interface with DDR SDRAM, DDR2 SDRAM, RLDRAM II, QDR SRAM, and QDRIISRAM memory devices. You can also use the DDR I/O registers as a

Name Required Descriptiondatain_l[] Yes Input data to be output to the padio port at the fallingedge of the outclock port. Input port [(WIDTH) - (1)..

Name Required Descriptionoe_out No Output enable for the bidirectional padio port. Outputport [WIDTH–1..0] wide. This port is available forStratix III

Date Version ChangesSeptember 2010 5.0 Added ports and parameters.June 2007 4.2 Updated for Quartus II software version 7.1:• Updated for Arria GX and

ALTDDIO Parameter SettingsThese tables list the parameter settings for the ALTDDIO IP cores.Table 1: ALTDDIO_IN Parameter SettingsThis table lists the

Parameter DescriptionAsynchronous clear and asynchronous set ports Select Use ‘aclr’ port for asynchronous clear (aclr).Select Use ‘aset’ port for asy

Parameter DescriptionWidth: (bits) Specify the width of the data buses.Asynchronous clear and asynchronous set ports Select Use ‘aclr’ port for asynch

Parameter DescriptionUse ‘dqsundelayedout’ port Creates undelayed output from the DQS pins. If youuse the ALTDDIO_BIDIR IP core for your DQSsignal in

Figure 2: Stratix II IOE in DDR Input I/O ConfigurationThis figure shows an IOE configured for DDR inputs for a Stratix or Stratix II device.CLRN/PRND

Figure 3: Output DDR I/O Path Configuration for Stratix Series and APEX II DevicesThis figure shows the IOE configuration for DDR outputs in Stratix s

Figure 4: Stratix IOE in DDR Output I/O ConfigurationThis figure shows the IOE configuration for DDR outputs in Stratix series devicesCLRN/PRND QENACh